The invention relates to a clock and data recovery circuit, and in particular to a clock and data recovery circuit employed in communication systems.
In a typical communication system, a transmitter generates data signals according to its clock and transmits the data signals to a receiver through channels. To correctly interpret the data signals, the receiver reads the data signals according to a clock synchronized with the transmitter's clock. The receiver thus requires a clock recovery system to recover the data signal from the transmitter. At least two clock recovery techniques are currently used. First, the transmitter's clock may be transmitted to the receiver on a channel parallel with the channel carrying the data signals. The receiver can then estimate the phase of the data signals from the phase of transmitter's clock. This technique however, is disadvantageous in that it requires an additional channel. Alternately, the phase of the data signals may be recovered directly from information carried in the data signals themselves.
FIG. 1 shows a conventional clock and data recovery circuit. The clock and data recovery circuit 1 comprises a control unit 10, a gated voltage controlled oscillator (GVCO) 11, a D flip-flop 12, and a phase locked loop (PLL) 13. The PLL 13 comprises a phase/frequency detector 130, a charge pump 131, a filter 132, and a GVCO 133. The control unit 10 controls the GVCO 11 to receive a data signal D1. The phase/frequency detector 130 of the PLL 13 receives a reference clock Cf1, and the filter 132 controls the GVCOs 11 and 133. The GVCOs 11 and 133 respectively output oscillated clocks CK1 and CK2 corresponding to the data signal D1. The D flip-flop 12 reads the data signal D1 according to the clock CK1, thus estimating the phase of the data signal D1 correctly.
In ideal conditions, the clock CK1 synchronizes with the clock CK2. However, since the processes of the GVCOs 11 and 133 may not match, difference between the phases of the locks CK1 and CK2 is increased with time, such that the D flip-flop 12 may incorrectly trigger the data signal D1.